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si838x data sheet bipolar digital field inputs for plcs and industrial i/o modules the si838x provides eight channels for 24 v digital field interface to either sinking or sourcing inputs with integrated safety rated isolation. in combination with a few external components, this provides compliance to iec 61131-2 switch types 1, 2, or 3. the input interface is based on silicon labs' ground-breaking cmos based led emulator technol- ogy which enables the bipolar capability (sinking or sourcing inputs) with no vdd re- quired on the field side. the output interface to the controller allows for low power opera- tion with 2.25 v operation capability. these products utilize silicon laboratories' propri- etary silicon isolation technology, supporting up to 2.5 kv rms withstand voltage. this technology enables high cmti (50 kv/s), lower prop delays and skew, reduced varia- tion with temperature and age, and tighter part-to-part matching. product options include parallel or serialized outputs. cascading capability for a total of 128 channels (16x si838x) is possible with serial output option. the si838x offers longer service life and dramatically higher reliability compared to opto-coupled input solutions. applications: ? programmable logic controllers ? industrial data acquisition ? distributed control systems ? cnc machines ? i/o modules ? motion control systems safety regulatory approvals: ? ul 1577 recognized ? up to 2500 v rms for one minute ? csa component notice 5a approval ? iec 60950-1 ? vde certification conformity ? vde 0884-10 ? cqc certification approval ? gb4943.1 key features ? bipolar digital interface with 24 v sinking or sourcing inputs ? eight total inputs in one package ? high data rates of up to 2 mbps ? safety rated integrated isolation of 2.5 kvrms ? low input current of 1 ma typ ? no vdd required on field side ? status leds on parallel outputs ? high electromagnetic immunity ? programmable debounce times of up to 100 ms ? transient immunity of 50 kv/s ? flow-through output configuration with eight outputs ? option for spi interface serialized outputs with daisy-chain capability ? wide 2.25 to 5.5 v vdd operation ? wide operating temperature range ? C40 to +125 c ? compliant to iec 61131-2 ? type 1, 2, 3 ? rohs-compliant packages ? qsop-20 silabs.com | smart. connected. energy-friendly. rev. 0.5
1. ordering guide table 1.1. si838x ordering guide ordering part number serial or parallel output number of high- speed channels low pass filter delay package type isolation rating si8380p-iu p 0 0 ms 20-qsop 2.5 kvrms si8382p-iu p 2 0 ms 20-qsop 2.5 kvrms si8384p-iu p 4 0 ms 20-qsop 2.5 kvrms SI8388P-IU p 8 0 ms 20-qsop 2.5 kvrms si8380s-iu s 0 0 ms 20-qsop 2.5 kvrms si8380pf-iu p 0 10 ms 20-qsop 2.5 kvrms si8382pf-iu p 2 10 ms 20-qsop 2.5 kvrms si8384pf-iu p 4 10 ms 20-qsop 2.5 kvrms si8380pm-iu p 0 30 ms 20-qsop 2.5 kvrms si8382pm-iu p 2 30 ms 20-qsop 2.5 kvrms si8384pm-iu p 4 30 ms 20-qsop 2.5 kvrms si8380ps-iu p 0 100 ms 20-qsop 2.5 kvrms si8382ps-iu p 2 100 ms 20-qsop 2.5 kvrms si8384ps-iu p 4 100 ms 20-qsop 2.5 kvrms si838x data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 0.5 | 1
2. functional description 2.1 theory of operation the operation of a si838x channel is analogous to that of a bipolar opto-coupler, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si838x channel is shown in the figure below. this product enables 24 v bipolar digital inputs to be connected to its input through a resistor network which acts as a voltage divider. the inputs can be sourcing or sinking type. to enable this functionality, there is a zero drop bridge and an led emulator at the front end that drives an ook (on-off key) modulator/demodulator across the capacitive isolation barrier. on the output side, the debounce block controls the amount of debounce desired. there are four debounce delay time options availa- ble: no delay, or delays of 10, 30, or 100 ms. in addition, the user can use the spi control to program user-specific debounce modes as explained in section 2.3.2 debounce filtering modes . the user-specific debounce programming is only available on the product option with spi interface. cmos isolation barrier modulator e hf transmitter demodulator vdd a b com debounce figure 2.1. simplified channel diagram 2.2 serial peripheral interface the si8380s includes a serial peripheral interface (spi) that provides control and monitoring capability of the isolated channels using a commonly available microcontroller protocol. the direct-mapped registers allow an external master spi controller to monitor the status of the eight plc channels, as well as to control the delay and filtering modes for the debounce of each channel. additionally, support is provided to easily daisy-chain up to sixteen plc devices. each of these daisy-chained devices may be uniquely addressed by one master spi controller. 2.2.1 spi register map the addressable spi registers include one eight-bit register to reflect the status of each of the eight channels, which is read-only. also, four additional registers provide two bits to specify the debounce delay, and two bits to specify the debounce filtering mode for each of the eight channels. these user accessible spi registers are illustrated in the following table. table 2.1. si838x spi register map name address access description chan_status 0x0 r current value of each of the eight plc channels {plc[7:0]} dbnc_mode0 0x1 r/w mode control bits for the first four channel debounce filters organized as: {md_ch3[1:0],md_ch2[1:0],md_ch1[1:0],md_ch0[1:0]} dbnc_mode1 0x2 r/w mode control bits for the second four channel debounce filters organized as: {md_ch7[1:0],md_ch6[1:0],md_ch5[1:0],md_ch4[1:0]} dbnc_dly0 0x3 r/w delay control bits for the first four channel debounce filters organized as: {dly_ch3[1:0],dly_ch2[1:0],dly_ch1[1:0],dly_ch0[1:0]} dbnc_dly1 0x4 r/w delay control bits for the second four channel debounce filters organized as: {dly_ch7[1:0],dly_ch6[1:0],dly_ch5[1:0],dly_ch4[1:0]} si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 2
2.2.2 spi communication transactions spi communication is performed using a four wire control interface. the four si838x device pins utilized for spi include: ? sclk (input) the spi clock ? nss (input) active low device select ? mosi (input) master-out-slave-in ? miso (output) master-in-slave-out additionally, a fifth wire sdi_thru (output) is provided as an si838x device pin to facilitate daisy chaining. an si838x spi communication packet is composed of three serial bytes. in this sequence, byte0 is the control byte, and specifies the operation to be performed as well as the device to be selected in a daisy chain organization. the cid[3:0] field should be set to all zeros by the spi master in non-daisy-chained operation. next, byte1 specifies the address of the internal si838x spi register to be accessed. the final byte in the packet consists of either the data to be written to the addressed si838x spi register (using mosi), or the data read from the addressed si838x spi register (using miso). details of the spi communication packet are presented in the following figure for an si838x spi write transaction. nss sclk mosi control[7:0] address[7:0] data[7:0] brct 1 - broadcast (write) 0 - only addressed part (write) ignored on reads r/wb 1 - read 0 - write ctl[5:4] reserved (set to 0,0) cid[3:0] daisy-chained part id (0) is closest to the master mosi. accomplished by decrementing the cid as it passes through to the next si838x device in the daisy chain on sdi_thru control byte 7 6 5 4 3 2 1 0 brct r/wb 0 0 cid[0] cid[1] cid[2] cid[3] address byte 7 6 5 4 3 2 1 0 a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] data byte 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] figure 2.2. spi communication packet structure, write operation and control byte structure the spi master will provide the timing of the signals and framing of the communication packets for all si838x spi inputs: nss, sclk, and mosi. data is communicated from the spi master to the si838x using the mosi signal. the nss and sclk signals provide the necessary control and timing reference allowing the si838x to discern valid data on the mosi signal. data is returned to the spi master by the si838x utilizing the miso signal only during the final byte of a three byte spi read communication packet. at all other times, the miso signal is tri-stated by the si838x. each of the eight bits for these three packets is captured by the si838x on eight adjacent rising edges of sclk. each frame of eight bits is composed within bounding periods where the device select, nss, is deasserted. upon the reception of the eight bits within a byte transaction, the deassertion of nss advances the byte counter within the internal si838x spi state machine. should the transmission of an eight bit packet be corrupted, either with the deassertion of nss before the eighth rising edge of sclk, or with the absence of the deassertion of nss after the eighth rising edge of sclk, the internal spi state machine may become unsynchronized with the master spi controller. to re-establish spi synchronization with the si838x, the spi master may, at any time, deassert the spi device select signal nss, and force a clock cycle on sclk. when unsynchronized, the rising edge of sclk when nss is deasserted (high) re-initializes the internal spi state machine. the si838x will then treat the immediately following eight bit spi transaction after nss is once again asserted as the first byte in a three byte spi communication packet. any preceding communication packet will be abandoned by the si838x at the point synchronization is lost, and the nss signal is deas- serted. this could occur at any point in the three byte sequence of a spi communication packet. one should note that abandoning a spi write operation early, even during the last byte of the three byte spi communication packet, will leave the destination register un- changed. however, if the number of sclk cycles exceeds eight during the last byte of the three byte spi write packet, the destination si838x register may be corrupted. to remedy both of these situations, it is recommended that such a corrupted write operation be re- peated immediately following resynchronization of the spi interface. si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 3
2.2.3 spi read operation referring to figure 2.2 spi communication packet structure, write operation and control byte structure on page 3 , in a spi read op- eration the control byte will only have bit6 set to a 1 in a single si838x device organization (no daisy-chaining). for the si838x, bit7 (the broadcast bit) is ignored during a read operation since only one device may be read at a time in either a single or daisy chained organi- zation. the second byte in the three byte read packet is provided by the spi master to designate the address of the si838x internal register to be queried. if the read address provided does not correspond to a physically available si838x internal register, all zeroes will be re- turned as the read value by the si838x. the read data is provided during the final byte of the three byte read communication packet to the querying master spi device utilizing the si838xs miso output, which remains tristated at all other times. the spi read operation timing diagram is illustrated in the figure below. nss sclk mosi control[7:0] address[7:0] readdata[7:0] miso figure 2.3. spi read operation 2.2.4 spi write operation again referring to figure 2.2 spi communication packet structure, write operation and control byte structure on page 3 , in a spi write operation the control byte may optionally have bit7 (the broadcast bit) set to a 1. during a spi write operation, the broadcast bit forces all daisy-chained si838x devices to update the designated internal spi register with the supplied write data, regardless of the si838x device being addressed using the cid[3:0] field of the control word. the second byte in the three byte write packet is provided by the spi master to designate the address of the si838x internal register to be updated. if the write address provided does not correspond to a physically available si838x internal register, no internal si838x spi register update will occur. the write data is provided by the spi master during the final byte of the three byte write communication packet. the si838x miso output remains tri-stated during the entire spi write operation. the spi write operation timing diagram is illustrated in the figure below. nss sclk mosi control[7:0] address[7:0] miso hiz writedata[7:0] figure 2.4. spi write operation si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 4
2.2.5 spi daisy chain organization the si838x provides the capability to easily interconnect multiple si838x devices on a common spi interface administered by a single spi master requiring no additional control signals. to accomplish this, the si838x includes the additional spi device output pin sdi_thru . connecting together multiple si838x devices in this manner utilizes the sdi_thru pin of one si838x device to feed the mosi pin of the next si838x device in the daisy-chain. all bits composing a spi communication packet are passed directly through by the si838x from the mosi input to the sdi_thru output unchanged, except for the cid[3:0] field of the control byte. the least significant four bits of the control byte in a spi communication packet, cid[3:0] , are dedicated to addressing one of up to sixteen si838x devices thus connected, with 0000 indicating the device whose mosi pin is fed directly by the spi master, 0001 the following si838x device, etc. as this bit field is passed through the si838x, it is decremented by one. this four bit field is placed in the control word by the spi master in reverse order, allowing the carry of the decrement to ripple into the next bit in the cid field as the bits of the control word proceed: cid[0] is placed at bit 3 and cid[3] placed at bit 0 of the control word. when a given si838x device in the daisy chain is presented with the cid[3:0] code of 0000 , it is activated as the one to be addressed. all remaining operations between the spi master and the si838x activated in this manner proceed as previously discussed for the case of the single si838x slave. the organization of an si838x system daisy-chained in this manner is depicted in the figure below. si838x[0] si838x[1] si838x[2] si838x[3] si838x[4] si838x[15] spi_master mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru figure 2.5. spi daisy chain organization from the preceding figure, and referring to figure 2.2 spi communication packet structure, write operation and control byte structure on page 3 , in order to read from si838x[1], the control word would be: control[7:0] = 0100_1000. similarly, in order to write to si838x[12], the control word would be: control[7:0] = 0000_0011. finally, if it were desired to update an internal spi register of all daisy-chained si838x devices, the control word would be: control[7:0] = 1000_0000. if the broadcast bit is zero during a write operation, only the si838x device being addressed using the cid[3:0] field of the control word in a daisy-chain organization will be updated. if the broadcast bit is one during a write operation, the cid[3:0] field is ignored, and all si838x devices connected in a daisy-chain will be updated. for non-daisy-chain operation, the cid[3:0] field should always be all ze- ros. note that there is a finite combinational delay associated with passing the mosi input pin of a given si838x to the sdi_thru output pin. as a result, the maximum possible sclk frequency will be reduced based on the number of si838x devices connected in a daisy-chain organization. si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 5
2.2.6 spi interface timing specification the timing diagram for the si838x spi interface is presented in the figure below. nss mosi sdi_thru miso sclk tdo1 tp tdo2 tsu2 th2 th1 tdz tsu1 rxbit<7> rxbit<7> txbit<7> txbit<6> txbit<5> txbit<0> rxbit<0> rxbit<5> rxbit<6> rxbit<0> rxbit<5> rxbit<6> tnss figure 2.6. spi timing diagram the timing specifications depicted in this figure apply to each byte of the three byte si838x spi communications packet. refer to the spi timing specifications in table 4.2 electrical characteristics on page 12 . although this discussion of the si838x spi interface has focused on a preferred organization (separate miso / mosi wires), other options are available with regard to the si838x control interface. possible si838x organizations include: ? miso/mosi wired operation ? miso/mosi may be two separate wires, or may be connected together if the spi master is capable of tri-stating its mosi during the data byte packet transfer of a read operation. ? multiple si838x devices interfaced in a non-daisy-chain format ? the spi master provides multiple nss signals, one for each of a multiple of si838x slaves. ? every si838x shares a single trace from its mosi input back to the spi master (the si838x sdi_thru signal is not utilized). 2.3 debounce filter the si838x includes a user programmable debounce filter, providing the user a mechanism to individually control the debounce behav- ior for each of the eight si838x isolation channels. user control of the debounce filter is accomplished via the included si838x spi inter- face. consequently, user control of this feature is available only on the serial interface accessible si838x device versions. the de- bounce filter is incorporated into the path of the input data stream allowing signal conditioning of the plc inputs. there are product options available with the parallel output interface with discrete debounce time constants of 0, 10, 30 or 100 ms these are only available on the low speed channels. the high speed channels have no debounce filtering (see 1. ordering guide for more details on part numbers). si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 6
2.3.1 debounce control registers the operation of the si838x debounce filters is controlled using r/w control registers mapped into the si838x spi address space. the details of these registers are covered in the si838x spi register map section of this document. the options available using these regis- ters are outlined in the following tables. for each of the eight plc channels, two data bits are allocated to control the debounce delay, and two bits are used to stipulate the debounce filtering mode. this consumes a total of 32 bits, which are allocated across four individ- ual si838x spi control registers of one byte each. table 2.2. debounce filter delay control dbnc_dly[1:0] delay (ms) comment 00 0 bypass debounce 01 10 10 30 11 100 table 2.3. debounce filter mode control dbnc_mode[1:0] filter mode comment 00 no filter simple trailing edge delay 01 low pass 1x leading edge si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 7
2.3.2 debounce filtering modes in addition to the user specifiable delays, three filtering modes are provided by the debounce function. like the debounce delay setting, these filtering modes may be unique for each of the eight si838x plc channels. the first of these three modes, corresponding to dbnc_mode[1:0] == 00 , employs only a simple trailing edge delay. in this mode, once the debounce filter input has been stable for the amount of time specified in the corresponding channels debounce delay setting, d, the output of the debounce filter assumes the value of the new debounce input. consequently, any glitches on the debounce input having a duration less than the channels debounce delay setting, d, will be suppressed. the second mode, corresponding to dbnc_mode[1:0] == 01 , performs a low pass filtering function on the input to the debounce filter. when the input to the debounce filter has assumed a new value, a counter begins counting toward the current delay setting, d. if before the count d is reached the debounce input returns to its previous state, this counter is decremented. assuming that the debounce filter input again assumes the new value before the counter is decremented back to 0 (i.e. glitch width is less than time the input had previ- ously assumed a new value), the counter incrementing resumes from a non-zero value. once this count has reached the designated delay, d, the debounce filter output assumes the value of the new debounce input. using this mechanism, any input glitches on the debounce input having a duration less than the channels debounce delay setting, d, will be suppressed. however unlike mode 0, when the debounce input returns to the new value after this glitch, credit is given for the time this new value was active before the glitch. the final mode, corresponding to dbnc_mode[1:0] == 1x , realizes a leading edge filtering function on the input to the debounce filter. internally, a counter is initialized to zero. when the input to the debounce filter changes, the output of the debounce filter immediately assumes the new value, and the counter is reset to the current delay setting, d. independent of what occurs on the input of the de- bounce filter, the counter begins decrementing after this change. when the counter again reaches zero, the current input of the de- bounce filter is compared to the current output of the filter. if they are they are different, again the debounce filter immediately assumes the new value. if they are the same, the output of the debounce filter will immediately change on the next new value of the debounce input. in either case, a change on the debounce output filter resets the counter to the current delay setting, d. a graphical depiction of the operation and characteristics for each these debounce filter modes is provided in the following figure. din d C t1 t2 dout i mode = 00 dout i a a b a a d t 1 + t2 (old) (old) dout i a d d a b mode = 01 mode = 1x figure 2.7. debounce filter modes timing diagram si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 8
2.4 typical operating characteristics 0.00 2.00 4.00 6.00 8.00 10.00 12.00 0.00 0.50 1.00 1.50 2.00 2.50 i f (ma) v f (v) si838x i f vs. v f over temperature -40c 0c 25c 125c 3.00 figure 2.8. input current vs. input voltage over temperature si838x data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 0.5 | 9
3. device operation table 3.1. truth table summary vdd input, ax/ahx output, bx/bhx p 1 on high p off low up 2 x low 1. p = powered (> uvlo). 2. up = unpowered (< uvlo). 3.1 device start-up during start-up, output bx/bhx are held low until the vdd is above the uvlo threshold for a time period of at least tstart. following this, the output is high when the current flowing from anode to cathode is > if(on). device startup, normal operation, and shutdown behavior is shown in the figure below. uvlo + uvlo - i f ( on ) i f v dd output : bx , bhx t start t phl t plh t phl i hys vdd hys t start figure 3.1. device start-up 3.2 undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. for example, the output side unconditionally enters uvlo when v dd falls below v dduvC and exits uvlo when v dd rises above v dduv+ . 3.3 layout recommendations to ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 vac) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 vac) by a certain distance (creepage/clearance). if a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 4.4 insulation and safety-related specifications 1 on page 15 and table 4.6 vde 0884-10 insulation characteristics 1 on page 16 detail the creepage/clearance and working voltage capabilities of the si838x. these tables also detail the component standards (ul1577, vde 0884, csa 5a), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. refer to the end-system specifica- tion (60950-1, etc.) requirements before starting any design that uses a digital isolator. si838x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 0.5 | 10
3.3.1 supply bypass the si838x family requires a 0.1 f bypass capacitor between vdd and gnd. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50C300 ? ) in series with the outputs if the system is excessively noisy. 3.3.2 output pin termination the nominal output impedance of an isolator driver channel is approximately 50 ?, 40%, which is a combination of the value of the on- chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. si838x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 0.5 | 11
4. electrical specifications table 4.1. recommended operating conditions parameter symbol min typ max unit v dd supply voltage v dd 2.25 5.5 v input data rate, low-speed channels (no debounce) d 250 kbps input data rate, (10 ms debounce) d 0.1 kbps input data rate, (30 ms debounce) d 0.033 kbps input data rate, (100 ms debounce) d 0.01 kbps input data rate, high-speed channels dh 2000 kbps input current i f(on) 1.0 20 ma operating temperature (ambient) t a C40 +125 c table 4.2. electrical characteristics v dd = 2.25 v C5.5 v; gnd = 0 v; t a = C40 to +125 c; typical specs at 25 c; v dd = 5 v dc parameter symbol test condition min typ max unit input current threshold i f(th) 460 606 950 a input current hysteresis 1 i hys 30 76 200 a input voltage threshold v f(th) 1.21 1.38 1.5 v input voltage hysteresis 2 v hys 30 73 130 mv input capacitance c i f = 100 khz 105 pf vdd undervoltage threshold v dduv+ vdd rising 1.93 2.06 2.19 v vdd undervoltage threshold v dduvC vdd falling 1.79 1.91 2.01 v vdd undervoltage hysterisis vdd hys 60 mv low level output voltage v ol iol = 4 ma 0.4 v high level output voltage v oh ioh = C4 ma vdd C 0.4 v output impedance z o 50 output current i sink vout = 0.1 v, 50 load 2.0 ma i source vout = vddC0.1 v, 50 load 2.0 ma dc supply current (all inputs 0 or 1) idd all inputs 0 2.8 4.8 6.7 ma all inputs 1 3.6 5.4 7.6 ma 125 khz supply current idd all inputs switching 3.7 5.5 7.7 ma 1 mhz (2 mbps) supply current si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 12
dc parameter symbol test condition min typ max unit idd all inputs switching 3.9 5.6 8.0 ma ac switching parameters (v dd = 5 v, c l = 15 pf) propagation delay, low to high t plh ahx channels 49 84 124 ns ax channels 3.8 4.1 4.6 s propagation delay, high to low t phl ahx channels 47 80 113 ns ax channels 3.75 4.15 4.55 s pulse width distortion pwd | tplh C tphl | ahx channels 6 50 ns ax channels 80 ns propagation delay skew t psk(p-p) part to part variation ahx channels 30 ns ax channels 80 ns channelCchannel skew t psk channel to channel variation ahx channels 30 ns ax channels 80 ns rise time t r 50 load 3.9 ns fall time t f 50 load 3.7 ns device startup time t start 150 s common mode transient immunity cmti see figure 4.1 common mode measurement circuit on page 14 . si838x high speed channels (ahx) 25 50 kv/s common mode transient immunity cmti see figure 4.1 common mode measurement circuit on page 14 . si838x low speed channels (ax) 200 300 kv/s serial data interface (see figure 2.6 spi timing diagram on page 6 .) clock rate 3 sclk 10 mhz cycle time (sclk) 4 t p 100 ns delay time, sclk fall to miso active tdo1 20 ns delay time, sclk fall to miso transition tdo2 20 ns delay time, nss rise to miso hi-z tdz 20 ns setup time, nss fall to sclk fall tsu1 25 ns hold time, sclk rise to nss rise th1 see figure 2.6 spi timing diagram on page 6 . 20 ns setup time, mosi to sclk rise tsu2 25 ns hold time, sclk rise to mosi transition th2 20 ns si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 13
dc parameter symbol test condition min typ max unit delay time between nss active tnss 200 ns propagation delay, tdthru mosi to sdi_thru 3 15 ns notes: 1. the current value at which device turns off is determined by i f(off) = i f(th) C i hys . 2. the voltage value at which the device turns off is determined by v f(off) = v f(th) C v hys . 3. see section 2.2.5 spi daisy chain organization . 4. for daisy chain operation, see spec for "propagation delay, mosi to sdi_thru" in this table. oscilloscope isolated reference voltages si838xp 2.25 to 5.5 v supply high voltage surge generator vcm surge output high voltage differential probe input signal switch input output isolated ground 2.2nf low-side resistor high-side resistor high low input output com gnd vdd figure 4.1. common mode measurement circuit si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 14
table 4.3. regulatory information (pending) 1 csa the si838x is certified under csa component acceptance notice 5a. for more details, see file 232873. 60950-1: up to 130 vrms reinforced insulation working voltage; up to 1000 vrms basic insulation working voltage. vde the si838x is certified according to vde0884. for more details, see file 5006301-4880-0001. vde 0884-10: 560 vpeak for basic insulation working voltage ul the si838x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 2500 vrms isolation voltage for single protection. cqc the si838x is certified under gb4943.1-2011. rated up to 130 vrms reinforced insulation working voltage; up to 1000 vrms basic insulation working voltage. note: 1. regulatory certifications apply to 2.5 kvrms rated devices that are production tested to 3.0 kvrms for 1 s. for more informa- tion, see 1. ordering guide . table 4.4. insulation and safety-related specifications 1 parameter symbol test condition qsop-20 unit nominal air gap (clearance) l(io1) 3.6 min mm nominal external tracking (creepage) l(io2) 3.6 min mm minimum internal gap (internal clearance) 0.008 mm tracking resistance (proof tracking index) pti iec60112 600 v erosion depth ed 0.057 mm resistance (input-output) 1 rio 10 12 capacitance (input-output) 1 cio f = 1 mhz 1 pf note: 1. to determine resistance and capacitance, the si838x is converted into a 2-terminal device. pins 1C10 are shorted together to form the first terminal, and pins 11C20 are shorted together to form the second terminal. the parameters are then measured be- tween these two terminals. si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 15
table 4.5. iec 60664-1 ratings parameter test condition qsop-20 basic isolation group material group i installation classification rated mains voltages < 150 vrms iCiv rated mains voltages < 300 vrms i-iii rated mains voltages < 400 vrms i-ii rated mains voltages < 600 vrms i-ii table 4.6. vde 0884-10 insulation characteristics 1 parameter symbol test condition characteristic unit qsop-20 maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method b1 (viorm x 1.875 = vpr,100%) production test, tm = 1 sec, (partial discharge < 5 pc) 1050 v peak transient overvoltage v iotm t = 60 s 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at ts, v io = 500 v r s >10 9 note: 1. this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si838x provides a climate classification of 40/125/21. table 4.7. iec safety limiting values 1 parameter symbol test condition max unit qsop-20 case temperature t s 150 c safety current i s ja = 105 c/w v f = 2.8 v, t j = 150 c, t a = 25 c 370 ma power dissipation p s 1.2 w note: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 4.2 (qsop-20) thermal derating curve, dependence of safety limiting values with case temperature per vde 0884 on page 17 . si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 16
table 4.8. thermal characteristics parameter symbol qsop-20 unit ic junction-to-air thermal resistance ja 105 c/w 398 389 370 0 50 100 150 200 250 300 350 400 450 0 20 40 60 80 100 120 140 160 temperature ( o c) vdd = 2.5 v vdd = 3.3 v vdd = 5.0 v safety limit current (ma) figure 4.2. (qsop-20) thermal derating curve, dependence of safety limiting values with case temperature per vde 0884 si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 17
table 4.9. absolute maximum ratings 1 parameter symbol min max unit storage temperature t stg C65 +150 c ambient temperature t a C40 +125 c junction temperature t j +150 c average forward input current i f(avg) 30 ma peak transient input current (< 1 s pulse width, 300 ps) i ftr 1 a input voltage, referred to com ax, ahx C0.5 7 v supply voltage v dd C0.5 7 v output voltage v out C0.5 v dd +0.5 v average output current i o(avg) 10 ma input power dissipation p i 480 mw output power dissipation (includes 3 ma per channel for status led) p o 484 mw total power dissipation p t 964 mw lead solder temperature (10 s) 260 c hbm rating esd 4 kv machine model esd 200 v cdm 500 v maximum isolation voltage (1 s) 3000 v rms note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. si838x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 18
5. applications 5.1 system level transitions with the si838x si838xp 2.2nf low-side resistor high-side resistor ahx input bhx output com gnd vdd r1 r2 v d field potential i in i d c1 24v dc ucontroller input gnd vdd v in field plc digital input module plc high speed channels only sensor or switch isolation barrier current limit resistor status lamp led r3 d2 figure 5.1. system level drawing of a high-speed channel on the si838xp with the supporting bill of materials the si838x combined with an appropriate input resistor network and indication led will produce a plc digital input module which ad- heres to the iec 61131-2 specification. resistors r1 and r2 set the transition voltages and currents for the system, as visualized in the figure below, while capacitor c1, is required only for high-speed channels and serves to improve cmti performance. further, resistor r3 is selected based on desired led, d2, brightness during a system on condition. v in i in tr1 device on system i-v curve tr2 device on v tr1 v tr2 device off device off hysteresis region hysteresis region i tr1 i tr2 figure 5.2. visualization of system level transitions when utilizing a si838x according to the recommended design process si838x data sheet applications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 19
5.2 iec 61131-2 compliance options iec 61131-2 articulates three types of digital inputs for plc sensing. each type category dictates boundary conditions on the system level input space, (v in , i in ), defining the range of values for which the module must output a logic low, a logic high, or transition between the two. more details on the specification can be found on the iec website: https://webstore.iec.ch/publication/4551 . the table below provides per-input type bill of materials recommendations for plug-n-play designs adhering to the specification or as a starting point for custom designs. these recommendations assume a resistor tolerance of 5%. table 5.1. si838x recommended input bill of materials and system level transition values 1 input resistor values nominal tr1 values nominal tr2 values plc digital input type r1 (?) r2 (?) i in (ma) v in (v) i in (ma) v in (v) type-1 2400 6200 1.18 8.70 1.07 7.97 type-2 390 1500 4.14 7.60 3.88 7.13 type-3 750 2700 2.45 7.98 2.27 7.44 note: 1. based on 24 v dc plc digital input types. 5.3 custom bill of materials a plc digital input module based on the si838x can have its transition values customized on a per-channel basis in accordance with the system level equations and tolerances. an extended discussion of this process and an example design are available in "an970: design guide for plc digital input modules using the si838x" . si838x data sheet applications silabs.com | smart. connected. energy-friendly. rev. 0.5 | 20
6. pin and package definitions the si838x consists of multiple dies in one package. each package and bond-out serves a customer need and may reflect multiple bond options. the following packages are defined: qsop-20. 1. ordering guide describes the part number and opn configuration quantities envisioned for these products. subsequent sections define the pins for each package type. 6.1 pin descriptions isolation barrier 1 2 3 4 5 6 9 10 19 18 17 16 15 ai/ah1 a2/ah2 a3/ah3 a4/ah4 com com a7/ah7 a8/ah8 b1/bh1 b2/bh2 b3/bh3 b4/bh4 vdd gnd b7/bh7 b8/bh8 7 8 a5/ah5 a6/ah6 b5/bh5 b6/bh6 si8380p/si8388p e e e e e e e e 14 12 11 20 13 isolation barrier 1 2 3 4 5 6 9 10 19 18 17 16 15 ah1 ah2 a1 a2 com com a5 a6 bh1 bh2 b1 b2 vdd gnd b5 b6 7 8 a3 a4 b3 b4 si8382p e e e e e e e e 14 12 11 20 13 isolation barrier 1 2 3 4 5 6 9 10 19 18 17 16 15 ah1 ah2 ah3 ah4 com com a3 a4 bh1 bh2 bh3 bh4 vdd gnd b3 b4 7 8 a1 a2 b1 b2 si8384p e e e e e e e e 14 12 11 20 13 a1 a2 a3 a4 com com a7 a8 a5 a6 isolation barrier 1 2 3 4 5 6 9 10 19 18 17 16 15 miso mosi nss sclk vdd gnd nc nc 7 8 sdithru nc si8380s e e e e e e e e 14 12 11 20 13 spi figure 6.1. si838x pin assignments si838x data sheet pin and package definitions silabs.com | smart. connected. energy-friendly. rev. 0.5 | 21
table 6.1. si838x pin descriptions pin name description a1 C a8 low-speed input channels ah1-ah8 high-speed input channels com common. can be connected to ground or 24 v b1-b8 low-speed output channels bh1-bh8 high-speed output channels vdd controller side power supply gnd controller side ground mosi spi, input sclk spi clock nss spi chip select sdithru spi serial data out for cascading multiple si838x (up to 16) miso spi, output si838x data sheet pin and package definitions silabs.com | smart. connected. energy-friendly. rev. 0.5 | 22
7. package outline the figure below illustrates the package details for the 20-pin qsop package. the table below lists the values for the dimensions shown in the illustration. figure 7.1. 20-pin qsop package outline si838x data sheet package outline silabs.com | smart. connected. energy-friendly. rev. 0.5 | 23
table 7.1. package dimensions dimension min max a 1.75 a1 0.10 0.25 a2 1.25 b 0.20 0.30 c 0.17 0.25 d 8.66 bsc e 6.00 bsc e1 3.91 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.20 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline m0-137, variation ad. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si838x data sheet package outline silabs.com | smart. connected. energy-friendly. rev. 0.5 | 24
8. land pattern the figure below illustrates the pcb land pattern details for the 20-pin qsop package. the table below lists the values for the dimen- sions shown in the illustration. figure 8.1. 20-pin qsop pcb land pattern table 8.1. 20-pin qsop pcb land pattern dimensions dimension feature mm c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 1. this land pattern design is based on ipc-7351 design rules for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc), and a card fabrication tolerance of 0.05 mm is assumed. si838x data sheet land pattern silabs.com | smart. connected. energy-friendly. rev. 0.5 | 25
9. top marking figure 9.1. si838x top marking (20-pin qsop) table 9.1. top marking explanation (20-pin qsop) line 1 marking: base part number ordering options see 1. ordering guide for more information. si838 = 8-ch plc input isolator x = # of high speed channels y = s, p s = serial outputs p = parallel outputs u = debounce option f = fast debounce, 10 ms m = slower debounce, 30 ms s = slow debounce, 100 ms line 2 marking: yy = year ww = workweek tttttt = mfg code assigned by the assembly house. corresponds to the year and workweek of the mold date and manufacturing code from assembly purchase order form. si838x data sheet top marking silabs.com | smart. connected. energy-friendly. rev. 0.5 | 26
10. document change list 10.1 revision 0.5 april 4, 2016 ? initial release. si838x data sheet document change list silabs.com | smart. connected. energy-friendly. rev. 0.5 | 27
table of contents 1. ordering guide .............................. 1 2. functional description ............................ 2 2.1 theory of operation ............................ 2 2.2 serial peripheral interface .......................... 2 2.2.1 spi register map ............................ 2 2.2.2 spi communication transactions ...................... 3 2.2.3 spi read operation ........................... 4 2.2.4 spi write operation ........................... 4 2.2.5 spi daisy chain organization ........................ 5 2.2.6 spi interface timing specification ...................... 6 2.3 debounce filter ............................. 6 2.3.1 debounce control registers ........................ 7 2.3.2 debounce filtering modes ......................... 8 2.4 typical operating characteristics ....................... 9 3. device operation ............................. 10 3.1 device start-up ............................. 10 3.2 undervoltage lockout ........................... 10 3.3 layout recommendations .......................... 10 3.3.1 supply bypass ............................. 11 3.3.2 output pin termination .......................... 11 4. electrical specifications .......................... 12 5. applications ............................... 19 5.1 system level transitions with the si838x .................... 19 5.2 iec 61131-2 compliance options ....................... 20 5.3 custom bill of materials .......................... 20 6. pin and package definitions ......................... 21 6.1 pin descriptions ............................. 21 7. package outline ............................. 23 8. land pattern .............................. 25 9. top marking ............................... 26 10. document change list .......................... 27 10.1 revision 0.5 .............................. 27 table of contents 28
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